1. Field of the Invention
The present invention relates to a controlling method for data processing circuit, a data latch circuit used for data processing unit, and the data processing circuit, more particularly to a controlling method for operating a data processing circuit in which a logical circuit is interposed between two data latch circuits, and to a construction of a high-speed data latch circuit.
2. Description of Related Art
FIG. 1 is a circuit diagram showing an example of construction of a conventional general data processing circuit. In the conventional data processing circuit, a logical circuit is connected in series between two data latch circuits, each of the two data latch circuits clocked by different two-phase clocks.
In FIG. 1, a data signal to be processed is input at an input terminal 1. A first data latch circuit 2 samples and latches the data signal input from the input terminal 1 synchronous with clock .phi.1. A logical circuit 3 logically processes the data signal output from the first data latch circuit 2, and outputs a data signal, which is the result of the logical processing, to a second data latch circuit 4. The second data latch circuit 4 samples and latches the data signal output from the logical circuit 3 in synchronism with clock .phi.2 and outputs it to an output terminal 5.
The construction of the first data latch circuit 2 is as follows.
The input terminal 1 is connected to an input end of a transmission gate (N-channel transistor) 2a which is a first gate, and an output end of the transmission gate 2a is connected to an input end of an inverter 2b. An output end of the inverter 2b is connected to an input end of an inverter 2c, and an output end of the inverter 2c is connected to an input end of a transmission gate 2d and becomes an output line to the logical circuit 3 as well. An output end of the transmission gate 2d is connected between the output end of the transmission gate 2a and the input end of the inverter 2b.
In addition, clock .phi.1 is given to the gate terminal of both the transmission gates 2a and 2d. Both inverters 2band 2c form a buffer circuit.
The logical circuit 3 consists of a plurality of NAND gates 3a, 3b and 3c, and the output end of the first data latch circuit 2 is connected to one input end of the NAND gate 3a, the output end of NAND gate 3a to one input end of NAND gate 3b, and the output end of NAND gate 3b to one input end of NAND gate 3c, the output end of the NAND gate 3c being an output line to the second data latch circuit 4. Logical circuit 3 inputs a data signal which is latched by the first data latch circuit 2 and outputs a data signal which has received a predetermined logical processing by the NAND gates 3a, 3b and 3c to the second data latch circuit 4.
The construction of the second data latch circuit 4 is as follows.
The output of logical circuit 3 is connected to an input end of a transmission gate (N-channel transistor) 4a and the output end of the transmission gate 4a is connected to an input end of an inverter 4b. The output end of the inverter 4b is connected to an input end of an inverter 4c, and the output end of the inverter 4c is connected to an input end of a transmission gate 4d and to an input end of an output buffer 4e. The output end of output buffer 4e becomes an output line of the second data latch circuit 4 which is connected to an output terminal 5. The output end of transmission gate 4d is connected between the output end of transmission gate 4a and the input end of inverter 4b.
In addition, clock .phi.2 is given to the gate terminals of both transmission gates 4a and 4d. In addition, inverters 4b and 4c form a buffer circuit.
The operation of such a conventional data processing circuit is as follows.
The first data latch circuit 2 samples a data signal given to the input terminal 1 when clock .phi.1 goes high and latches the data signal until clock .phi.1 goes high in a following clock cycle. Logical circuit 3 processes and outputs the data signal which is outputted from the first data latch circuit 2 until clock .phi.2 goes high following clock .phi.1 going high. The second data latch circuit 4 samples data output from logical circuit 3 when clock .phi.2 goes high and latches the signal until clock .phi.2 goes low, then high, and then outputs the signal to the output terminal 5.
That is, the data processing circuit shown in FIG. 1 samples an input data signal supplied to the input terminal 1, when clock .phi.1 is high, logical-processes it and outputs it to the output terminal 5 in synchronism with a rising edge of clock following clock .phi.1 being high.
Next, explanation will be given on the operation of a data latch circuit with the first data latch circuit 2 as an example.
When clock .phi.1 is high, transmission gate 2a is active, so the data signal given to the input terminal passes through transmission gate 2a to inverter 2b. As the inverter 2b inverts the data signal transmitted after passing through transmission gate 2a and outputs it, the negative logic of the data signal is transmitted to inverter 2c. Moreover, as inverter 2c inverts the data signal transmitted from inverter 2b and outputs it, the output of inverter 2c becomes positive logic of the data signal and becomes the output of the first data latch circuit 2.
In addition, when clock .phi.1 is high, transmission gate 2d becomes inactive, and the output of inverter 2c is not returned to the input end of inverter 2b. Accordingly, the output of the inverter 2c never collides with the output of transmission gate 2a.
When clock .phi.1 goes from high to low transmission gate 2a becomes inactive, and transmission gate 2d becomes active. Accordingly, regardless of the data signal input to input terminal 1, the output of inverter 2c is returned to the input end of inverter 2b through transmission gate 2d, so the output of inverter 2c, that is, the output of the first data latch circuit 2, is held while clock .phi.1 is low. In other words, when clock .phi.1 is high, the data signal input to input terminal 1 is latched by the first data latch circuit 2.
When clock .phi.1 goes high, the aforementioned state is canceled, and the first data latch circuit 2 changes to a state where the data signal input to input terminal 1 is output to logical circuit 3 again.
The second data latch circuit 4 operates in the same way.
Next, explanation will be made of the timing in the case where the circuit shown in FIG. 1 operates at a basic clock rate of 50 MHz with reference to the timing chart shown in FIG. 2. In addition, the time required for passing each state of the logical gate is assumed to be 2 ns.
As the basic clock shown in FIG. 2(a) is -50 MHz, one cycle thereof is 20 ns. Both clocks .phi.1 and .phi.2 shown in FIG. 2(b) and (c) are generated as non-overlap clocks, each obtained by frequency-dividing the basic clock, and each one cycle is 40 ns.
FIG. 2(d) shows a data waveform at a node 31 being between input terminal 1 and the first data latch circuit 2. FIG. 2(e) shows an output waveform of the first data latch circuit 2 at node 32 being between the first data latch circuit 2 and logical circuit 3. FIG. 2(f) shows an output waveform of logical circuit 3 at node 33 being between logical circuit 3 and second data latch circuit 4. FIG. 2(g) shows an output waveform of second data latch circuit 4 at node 34 being between second data latch circuit 4 and output terminal 5.
At the rising edge of clock .phi.1, the waveform of the data signal at node 31 shown in FIG. 2(d) given to input terminal 1 is output from first data latch circuit 2 after 6 ns, and becomes the waveform of node 32 shown in FIG. 2(e). The waveform of node 32 shown in FIG. 2(e) is output from logical circuit 3 after 6 ns and clock .phi.1 goes low, and becomes the waveform of node 33 shown in FIG. 2(f).
Here, to the other ends of NAND gates 3a, 3b and 3cof logical circuit 3, all high level signals are assumed to be input.
When clock .phi.2 goes high, the data signal output from logical circuit 3 is taken into second data latch circuit 4, and the waveform of node 34 shown in FIG. 2(g) is output after 8 ns from the rising edge of clock .phi.2.
As aforementioned, in the conventional data processing circuit, clock periods are allocated so that input terminal 1 may operate while clock .phi.1 is high, logical circuit 3 may operate while both clocks .phi.1 and .phi.2 are low, and second data latch circuit 4 may operate while clock .phi.2 is high. Accordingly, the data processing circuit processes one data input every two clock cycles of the basic clock.
In order to operate such a data processing circuit at high speeds, it is required to raise clock frequency. Recently, however, clock frequencies have risen as much as possible, and it is difficult to raise clock frequencies more than that of the present state. Moreover, a high frequency clock is accompanied with difficulty in system construction.